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Issue Date
Title
Author(s)
2016
A rule-based approach for minimizing power dissipation of digital circuits
Das, Subrata
;
Dasgupta, Partha Sarathi
;
Fišer, Petr
;
Ghosh, Sudip
;
Das, Debesh Kumar
2017
Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff
Pal, Debasis
;
Pramanik, Abir
;
Dasgupta, Partha Sarathi
;
Das, Debesh Kumar
2016
Delay estimates for graphene nanoribbons: A novel measure of fidelity and experiments with global routing trees
Das, Subrata
;
Das, Soma K.
;
Majumder, Adrija
;
Dasgupta, Partha Sarathi
;
Das, Debesh Kumar
Discover
Author
3
Dasgupta, Partha Sarathi
2
Das, Subrata
1
Das, Soma K.
1
Fišer, Petr
1
Ghosh, Sudip
1
Majumder, Adrija
1
Pal, Debasis
1
Pramanik, Abir
Subject
1
Carbon nanomaterial
1
CMOS
1
De-Compaction
1
Double Patterning Lithography
1
dynamic power
1
Fidelity
1
Garphene nanoribbon
1
Global routing
1
Hexagonal steiner tree
1
Logic optimization
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Date issued
2
2016
1
2017
Has File(s)
3
false