Please use this identifier to cite or link to this item: https://ir.iimcal.ac.in:8443/jspui/handle/123456789/474
Title: A Rule-based Method for Minimizing Power Dissipation by Reducing Switching Activity of Digital Circuits
Authors: Das, Subrata
Ghosh, Sudip
Dasgupta, Parthasarathi
Sensarma, Samar
Keywords: Switching Activity
low-power VLSI circuits
CMOS
Power dissipation
dynamic power
electromigration
Issue Date: 1-May-2015
Publisher: INDIAN INSTITUTE OF MANAGEMENT CALCUTTA
Series/Report no.: WORKING PAPER SERIES;WPS No. 761 May 2015
Abstract: Minimization of power dissipation of VLSI circuits is one of the major concerns of recent digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher clock frequencies and larger die sizes. The primary contributors to power dissipation in digital circuits include leakage power; short-circuit power, and switching power. Of these, power dissipation due to circuit switching activity constitutes the major component. As such, an effective mechanism to minimize power loss in such cases often involves the minimization of switching activity. In this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of digital circuits at logic optimization stage. The proposed algorithm is empirically tested for several standard digital circuits with Synopsis EDA tool and results obtained are quite encouraging.
URI: https://ir.iimcal.ac.in:8443/jspui/handle/123456789/474
Appears in Collections:2015

Files in This Item:
File Description SizeFormat 
wps_761.pdf321.35 kBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.