Please use this identifier to cite or link to this item: https://ir.iimcal.ac.in:8443/jspui/handle/123456789/420
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dc.contributor.authorDas, Subrata
dc.contributor.authorDasgupta, Parthasarathi
dc.contributor.authorSensarma, Samar
dc.date.accessioned2017-05-19T11:49:09Z
dc.date.accessioned2021-08-26T03:57:27Z-
dc.date.available2017-05-19T11:49:09Z
dc.date.available2021-08-26T03:57:27Z-
dc.date.issued2012-09-01
dc.identifier.urihttps://ir.iimcal.ac.in:8443/jspui/handle/123456789/420-
dc.description.abstractThe use of multi-valued logic in VLSI circuits can reduce the chip area significantly. Moreover, there are several additional advantages of using multi-valued logic in VLSI over the conventional Binary logic, such as energy efficiency, cost-effectiveness and so on. It has been shown that Base-3 number system is nearly optimal for computation. This paper is composed of two parts. In the first part of this paper we have studied some existing logical operation on ternary number system. We have also discussed some of the existing arithmetic operations using ternary number system. Some new algorithms for arithmetic operations have also been proposed, and shown to be quite efficient in terms of time complexity. In the second part of this paper we have discussed a special class of Boolean function, known as Rotation Symmetric Boolean Function in base-3. Algorithms for Rotation symmetric Boolean Function in base-3 is also proposed in this paper.en_US
dc.language.isoen_USen_US
dc.publisherINDIAN INSTITUTE OF MANAGEMENT CALCUTTAen_US
dc.relation.ispartofseriesWORKING PAPER SERIES;WPS No. 714/ September 2012
dc.subjectTernary numberen_US
dc.subjecttriten_US
dc.subjectarithmeticen_US
dc.subject3-valued logicen_US
dc.subjectVLSIen_US
dc.titleArithmetic Algorithms for Ternary Number Systemen_US
dc.typeWorking Paperen_US
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