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DC Field | Value | Language |
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dc.contributor.author | Roy, Ram Babu | |
dc.contributor.author | Saha, Debashis | |
dc.contributor.author | Dasgupta, Parthasarathi | |
dc.date.accessioned | 2017-05-09T06:32:16Z | |
dc.date.accessioned | 2021-08-26T03:55:37Z | - |
dc.date.available | 2017-05-09T06:32:16Z | |
dc.date.available | 2021-08-26T03:55:37Z | - |
dc.date.issued | 2010-08-01 | |
dc.identifier.uri | https://ir.iimcal.ac.in:8443/jspui/handle/123456789/369 | - |
dc.description.abstract | We often confront with optimization problems that require optimizing multiple objectives. Such multi-objective optimization problems are often non-linear in nature and are hard to solve. In such situations conventionally heuristic methods are used to arrive at some reasonably good solutions. VLSI standard cell placement problems traditionally have to handle multiple objectives such as area, delay, thermal distribution and so on, to arrive at a reliable design. One of the key concerns in this area is to simultaneously (i) optimize the thermal distribution of the heat dissipated by the logic gates on the chip and (ii) minimize the total wirelength required to interconnect these gates. This in turn helps in reducing the chances of occurrence of hot spots on the chip, on-chip delay and the total chip area. Optimizing these objectives individually is known to be NP-hard and hence simultaneous optimization of the two objectives is a challenging problem. In this work, we have also proposed a game-theoretic formulation to the problem and developed some novel heuristic algorithms for solving this problem. The proposed algorithms have been implemented, and the experimental results are quite encouraging | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | INDIAN INSTITUTE OF MANAGEMENT CALCUTTA | en_US |
dc.relation.ispartofseries | WORKING PAPER SERIES;WPS No. 661/ August 2010 | |
dc.subject | optimization methods | en_US |
dc.subject | Integrated Circuit layout design | en_US |
dc.subject | game theory | en_US |
dc.subject | heuristic methods | en_US |
dc.title | Novel Approach for Solving Multi-objective Optimization Problems: A Case of VLSI Thermal Placement | en_US |
dc.type | Working Paper | en_US |
Appears in Collections: | 2010 |
Files in This Item:
File | Description | Size | Format | |
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wps-661_1.pdf | 130.17 kB | Adobe PDF | View/Open |
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