On some selected issues in VLSI Interconnect Layouts in the nanometer range

Abstract

The advent of deep sub-micron and nanometric regime for CMOS semiconductor technology has resulted in several restrictions in the physical design of VLSI circuits primarily through constraints imposed by interconnects. These constraints typically include the interconnect delay, congestion, cross-talk, power dissipation and others. These issues have to be considered in the physical design of VLSI circuits. For a specific set of design goals, faster design convergence is often achieved by considering estimates of some or all of these parameters in the physical synthesis and logic synthesis stages. Thus, accurate estimation of these parameters have direct impact on issues such as convergence, performance, yield and manufacturability of chips, and there is immense scope of research in design and performance of interconnects. In addition to these, efforts are on for exploration and use of routing architectures which are different from the traditional Manhattan architecture. In this survey, we attempt to provide a brief overview of some of the select areas of the state-of-the art research on interconnect routing in the deep sub-micron and nanometer range.