Please use this identifier to cite or link to this item: https://ir.iimcal.ac.in:8443/jspui/handle/123456789/1724
Title: A novel wire planning technique for optimum pin utilization in digital microfluidic biochips
Authors: Roy, Pranab
Bhattacharya, Samadrita
Bhattacharyay, Rupam
Imam, Firdousi Jamil
Rahaman, Hafizur
Dasgupta, Partha Sarathi
Keywords: Algorithms
Digital microfluidics
Droplet routing
Electrodes
Multiphasing
Optimization
Pin constraints
Wire planning
Issue Date: 2014
Publisher: SCOPUS
Proceedings of the IEEE International Conference on VLSI Design
Abstract: Droplet based micro fluidic technology in recent years is reckoned as a major driving force for the development of new generation of Lab-on-chip devices. Such devices known as digital micro fluidic biochips are capable of manipulating discrete nanolitre volumes of droplets on a 2D planar array of electrodes. Due to their inherent nature of reconfigurability and scalability these devices are designed to be employed for large scale integration of multiple bioassays within the same grid. In order to enable such applications increasing number of control pin requirements together with high wire planning complexity becomes a major problem. In this paper we have proposed new techniques for interconnection wire routing for the control electrodes operating at identical time sequence. We have defined a double layer dual wire system running in parallel along two separate planes in mutually perpendicular directions. We further proposed an algorithm to develop a feasible wire plan for a given layout with an aim to optimize the overall number of pin count. Multiphasing on same pin has been proposed to resolve the issue of wire planning in cases of cross contamination at any particular site. The proposed technique has been employed in layouts using test benches for Benchmark suite III and selective test benches for benchmark suite I. The objective was to obtain a feasible wire plan with optimum pin utilization and enhanced route performance. The results obtained from simulation of the proposed algorithm on the test benches (mentioned earlier) are found to be encouraging. © 2014 IEEE.
Description: Roy, Pranab, School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India; Bhattacharya, Samadrita, School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India; Bhattacharyay, Rupam, School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India; Imam, Firdousi Jamil, School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India; Rahaman, Hafizur, School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India; Dasgupta, Partha Sarathi, Indian Institute of Management, Calcutta, India
ISSN/ISBN - 10639667
pp.510-515
DOI - 10.1109/VLSID.2014.95
URI: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84894542348&doi=10.1109%2fVLSID.2014.95&partnerID=40&md5=da77f505b336c4b79dca269c27ab5e7b
https://ir.iimcal.ac.in:8443/jspui/handle/123456789/1724
Appears in Collections:Management Information Systems

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