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DC Field | Value | Language |
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dc.contributor.author | Pal, Debasis | |
dc.contributor.author | Pramanik, Abir | |
dc.contributor.author | Dasgupta, Partha Sarathi | |
dc.contributor.author | Das, Debesh Kumar | |
dc.date.accessioned | 2021-08-26T06:23:43Z | - |
dc.date.available | 2021-08-26T06:23:43Z | - |
dc.date.issued | 2017 | |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85034760401&doi=10.1109%2fISVDAT.2016.8064875&partnerID=40&md5=3329aeba7f674e4b0ae0c7106d08f071 | |
dc.identifier.uri | https://ir.iimcal.ac.in:8443/jspui/handle/123456789/1669 | - |
dc.description | Pal, Debasis, Department of CSE, Jadavpur University, Kolkata, India; Pramanik, Abir, Department of CSE, Jadavpur University, Kolkata, India; Dasgupta, Partha Sarathi, MIS Group, Indian Institute of Management Calcutta, Kolkata, India; Das, Debesh Kumar, Department of CSE, Jadavpur University, Kolkata, India | |
dc.description | DOI - 10.1109/ISVDAT.2016.8064875 | |
dc.description.abstract | A layout decomposition in Double Patterning Lithography (DPL) is considered to be potential for processing nodes at or below 32 nm. In this method, two features are assigned different colors corresponding to different exposures if the spacing between them is less than a minimum value defined by design-specific rules. In general, there are cases where such different colors assignment may not be possible even though the inter-feature spacing is less than the specified minimum. This condition is often known as color conflict of adjacent features. Color conflicts are traditionally resolved by splitting the features. This problem is often modeled as a graph-theoretic problem, with color conflicts identified as odd-cycle detection, and the duplication of vertices of the graph arising out of splitting of features of a layout. However, for a given layout, the splitting of features may not always be desirable or even feasible. In this paper, we propose a merge-only technique with conservative application of de-compaction so that the overall area of the layout is minimally affected. We consider layouts having rectilinear features present in the layout and apply the proposed algorithm to obtain a DPL-compliant layout with selective use of stitches keeping the overall layout area fixed. Experimental results with some standard layouts demonstrate the effectiveness of the proposed algorithm. © 2016 IEEE. | |
dc.publisher | SCOPUS | |
dc.publisher | 2016 20th International Symposium on VLSI Design and Test, VDAT 2016 | |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
dc.subject | De-Compaction | |
dc.subject | Double Patterning Lithography | |
dc.subject | Overlay Error | |
dc.subject | Stitch | |
dc.title | Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff | |
dc.type | Conference Paper | |
Appears in Collections: | Management Information Systems |
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