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|Title:||Crosstalk aware coupled line delay tree construction for on-chip interconnects|
Dasgupta, Partha Sarathi
|Keywords:||Coupled line delay model|
Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
|Abstract:||Crosstalk noise dominates in deep submicron VLSI design as interconnects are more closely placed over a small layout area. Signal response and signal integrity is largely affected by crosstalk delay and noise. In this paper, we propose a coupled line delay model for on-chip interconnects during global routing, with crosstalk between wires as the parameter to be optimized. Our proposed model is influenced by moment matching model of a transmission line. We propose an algorithm for crosstalk aware delay tree construction, optimizing the effect of crosstalk delay in the tree structure by employing a cut and join strategy. Experiments are done on some benchmark instances with different technology parameters, and simulation results obtained are quite encouraging. © 2011 IEEE.|
|Description:||Samanta, Tuhina, Bengal Engineering and Science University, Howrah P.O. Botanic Garden, Howrah 711103, WB, India; Khatun, Sanoara, Bengal Engineering and Science University, Howrah P.O. Botanic Garden, Howrah 711103, WB, India; Rahaman, Hafizur, Bengal Engineering and Science University, Howrah P.O. Botanic Garden, Howrah 711103, WB, India; Dasgupta, Partha Sarathi, Indian Institute of Management Calcutta, Kolkata 700104, WB, India|
ISSN/ISBN - 978-161284914-0
DOI - 10.1109/ISQED.2011.5770750
|Appears in Collections:||Management Information Systems|
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