Obstacle aware routing in 3D integrated circuits

Abstract

Progressive scaling of technology node has serious impacts on the performance of VLSI circuits. A major influencing factor is the dominance of interconnect delay, and its associated effects such as excessive power consumption, signal integrity issues, and so on. 3D architectures were proposed as an alternative to the classical 2D architectures with certain specific advantages such as reduced interconnect lengths, and hence the delay. However, negative issues like through-silicon vias (TSVs), excessive heating effects etc also come into play. Routing problem in 3D ICs becomes even more complicated in presence of obstacles across the routing layers. In this paper, in an attempt to gain a better insight of the use of interconnects in 3D architectures,we propose a method for routing of nets in the 3D architecture with the presence of obstacles across the routing layers, and perform empirical study in terms of total interconnection lengths across the layers as well as the inter-layer cost involved in TSV. © 2012 Springer-Verlag.