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DC Field | Value | Language |
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dc.contributor.author | Gupta, Partha Sarathi | |
dc.contributor.author | Burman, Debasree | |
dc.contributor.author | Das, Jayita | |
dc.contributor.author | Brahma, Madhuchhanda | |
dc.contributor.author | Rahaman, Hafizur | |
dc.contributor.author | Dasgupta, Partha Sarathi | |
dc.date.accessioned | 2021-08-26T06:23:37Z | - |
dc.date.available | 2021-08-26T06:23:37Z | - |
dc.date.issued | 2012 | |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84874417631&doi=10.1109%2fCODIS.2012.6422158&partnerID=40&md5=219a2d16c985025c22cee780c8e17b80 | |
dc.identifier.uri | https://ir.iimcal.ac.in:8443/jspui/handle/123456789/1567 | - |
dc.description | Gupta, Partha Sarathi, Bengal Engineering and Science University, Shibpur, Howrah, India; Burman, Debasree, Bengal Engineering and Science University, Shibpur, Howrah, India; Das, Jayita, Bengal Engineering and Science University, Shibpur, Howrah, India; Brahma, Madhuchhanda, Bengal Engineering and Science University, Shibpur, Howrah, India; Rahaman, Hafizur, Bengal Engineering and Science University, Shibpur, Howrah, India; Dasgupta, Partha Sarathi, Indian Institute of Management, Calcutta, India | |
dc.description | ISSN/ISBN - 978-146734698-6 | |
dc.description | pp.149-152 | |
dc.description | DOI - 10.1109/CODIS.2012.6422158 | |
dc.description.abstract | An analytical model for the 2D potential distribution in sub-threshold regime of operation of a Double Gate Junctionless FET (DG-JL FET) structure is developed. Threshold voltage is computed by computing the minimum value of channel potential. The model predicts the threshold voltage of the device with reasonable accuracy. © 2012 IEEE. | |
dc.publisher | SCOPUS | |
dc.publisher | Proceedings of the 2012 International Conference on Communications, Devices and Intelligent Systems, CODIS 2012 | |
dc.subject | Junctionless FET | |
dc.subject | SCE | |
dc.subject | TCAD | |
dc.subject | Threhold voltage | |
dc.title | Modeling the channel potential and threshold voltage of a fully depleted Double Gate Junctionless FET | |
dc.type | Conference Paper | |
Appears in Collections: | Management Information Systems |
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