Please use this identifier to cite or link to this item: https://ir.iimcal.ac.in:8443/jspui/handle/123456789/1567
Title: Modeling the channel potential and threshold voltage of a fully depleted Double Gate Junctionless FET
Authors: Gupta, Partha Sarathi
Burman, Debasree
Das, Jayita
Brahma, Madhuchhanda
Rahaman, Hafizur
Dasgupta, Partha Sarathi
Keywords: Junctionless FET
SCE
TCAD
Threhold voltage
Issue Date: 2012
Publisher: SCOPUS
Proceedings of the 2012 International Conference on Communications, Devices and Intelligent Systems, CODIS 2012
Abstract: An analytical model for the 2D potential distribution in sub-threshold regime of operation of a Double Gate Junctionless FET (DG-JL FET) structure is developed. Threshold voltage is computed by computing the minimum value of channel potential. The model predicts the threshold voltage of the device with reasonable accuracy. © 2012 IEEE.
Description: Gupta, Partha Sarathi, Bengal Engineering and Science University, Shibpur, Howrah, India; Burman, Debasree, Bengal Engineering and Science University, Shibpur, Howrah, India; Das, Jayita, Bengal Engineering and Science University, Shibpur, Howrah, India; Brahma, Madhuchhanda, Bengal Engineering and Science University, Shibpur, Howrah, India; Rahaman, Hafizur, Bengal Engineering and Science University, Shibpur, Howrah, India; Dasgupta, Partha Sarathi, Indian Institute of Management, Calcutta, India
ISSN/ISBN - 978-146734698-6
pp.149-152
DOI - 10.1109/CODIS.2012.6422158
URI: https://www.scopus.com/inward/record.uri?eid=2-s2.0-84874417631&doi=10.1109%2fCODIS.2012.6422158&partnerID=40&md5=219a2d16c985025c22cee780c8e17b80
https://ir.iimcal.ac.in:8443/jspui/handle/123456789/1567
Appears in Collections:Management Information Systems

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.