An internet-based IP protection scheme for circuit designs using linear feedback shift register-based locking

Abstract

Due to emerging trend of design reuse in VLSI circuits, the intellectual property (IP) of design faces serious challenges like forgery, theft, misappropriation etc. These increasing risks of design IP stored in design repositories, or the threat of hacking the same during its Internet-based transmission, mandates design file encryption and its appropriate watermarking. In this paper, we propose a novel Internetbased scheme to tackle this problem. Input to the proposed scheme is a generic graph corresponding to a digital system design. Watermarking of the graph and its encryption are achieved using a new linear feedback shift register(LFSR)-based locking scheme. The proposed scheme makes unauthorized disclosure of valuable designs almost infeasible, and can easily detect any alteration of the design file during transmission. It ensures authentication of the original designer as well as non-repudiation between the seller and the buyer. Empirical evidences on several well-known benchmark problem sets are encouraging.